1. Field of the Invention
The present invention concerns an SRAM memory structure. The present invention can be embodied, for example, as an SRAM memory cell structure having a thin film transistor (hereinafter sometimes simply referred to as "TFT").
2. Description of the Related Art
As an SRAM cell structure in the prior art, a TFT load type SRAM memory cell structure which is a cell structure comprising, for example, a thin film transistor has been known. FIG. 1 shows a substrate structure of a unit cell as one example of a usual CMOS-SRAM memory cell structure in which a word transistor and a driver transistor are formed on an Si substrate, TFT is laid over the upper layer portion thereof as a load device, a word line 1 is disposed at the center of the cell, and two driver transistors (electrodes of which are shown by 2 and 3) are disposed on both sides thereof substantially in parallel and in a point-to-point symmetry with respect to the center of the cell, to each other.
FIG. 2 shows a memory unit cell circuit. In FIG. 2, transistors 11, 16 are word transistors, transistors 12, 15 are driver transistors and transistors 13, 14 are TFT constituting load transistors. A portion A1 comprising the transistors 11, 12 and a portion A2 comprising the transistors 15, 16 in the figure are formed on a Si substrate.
In highly integrated memories since 4MSRAM, it is generally practiced to form word transistors and driver transistors on a Si substrate and constitute load transistors as PMOS-TFT, and FIG. 1 shows a structure for one example thereof. FIG. 1 shows only the arrangement of gate electrodes of the word transistors and the driver transistors, and contacts relevant to them. That is, an electrode 1 is a word line (corresponding to the word transistors 11, 16 in FIG. 2), electrodes 2, 3 are driver transistors (corresponding to the driver transistors 12, 15 in FIG. 2), and a portion 4 in FIG. 1 is an inter-device separation region for separating them. A signal taken out of a node contact 5 passes through the word transistor 1 and taken out of a bit contact 6 by way of a diffusion layer below the contact portion of the electrode 2. The signal is shown by S in the figure.
Now considering the stability of the memory cell, the stability is generally increased either by increasing the channel width of the driver transistor (shown by Wd) or by increasing the channel length (shown by Lw) of the word transistor.
The electrodes 1, 2 and 3 were formed in one identical step but, as can be seen from FIG. 1, the cell area is increased concerned with a design rule if the stability is intended to be improved. Further, in this existent example, a signal transmitted from the memory node 5 to the bit contact 6 has to be passed through a diffusion layer below the gate electrode 2 of the driver transistor. Therefore, this leads to problems such as increase of resistance and capacitance and difficulty for ensuring insulation voltage withstand or the like.
Further, for preparing, for example, an SRAM cell, contact hole forming steps have to be repeated for twice or three times in order to form two memory nodes in the cell and, accordingly, such increased number of steps result in the reduction of the yield.
For instance, in a case of a TFT load type cell that has been gradually employed recently in 4MSRAM cell, a method of forming at first a node contact between two driver transistors by way of a contact hole forming step, then forming a contact connecting the node and a node between two TFTs in the same way and, further, forming a node contact between the TFTs is used, which increases the number of steps.